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HD74AC194
4-bit Bidirectional Unviersal Shift Register
REJ03D0259-0200Z (Previous ADE-205-379 (Z)) Rev.2.00 Jul.16.2004
Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load, shift right (in the direction Q0 toward Q3); shift left; inhibit clock (do nothing). Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial date for this mode is entered at the shift right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high.
Features
* Asynchronous Master Reset * Hole (Do Nothing) Mode * Outputs Source/Sink 24 mA * Ordering Information
Part Name HD74AC194FPEL HD74AC194RPEL Package Type SOP-16 pin (JEITA) Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-16DAV FP RP EL (2,000 pcs/reel) EL (2,500 pcs/reel)
SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code.
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC194
Pin Arrangement
MR 1 DSR 2 P0 3 P1 4 P2 5 P3 6 DSL 7 GND 8 (Top view) 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 CP 10 S1 9 S0
Logic Symbol
DSR P0 S0 S1 CP MR Q0
P1
P2
P3
DSL
Q1
Q2
Q3
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC194
Pin Names
S0, S1 P0 to P3 DSR DSL CP MR Q0 to Q3 Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs
Logic Diagram
DSL P3 P2 P1 P0 DSR
S0
S1
D C CQ CL CL
D C CQ CL CL
D C CQ CL CL
D C CQ CL CL
CP MR
Q3
Q2
Q1
Q0
Mode Select Table
Operating Mode Reset Hold Shift Left Shift Right L H H H H H MR X L H H L L S1 X L L L H H Inputs S0 DSR X X X X L H X X L H X X Output DSL X X X X X X Pn L q0 q1 q1 L H Q0 L q1 q2 q2 q0 q0 Q1 L q2 q3 q3 q1 q1 Q2 L q3 L H q2 q2 Q3
Parallel Load H H H X X pn p0 p1 p2 p3 H : HIGH Voltage Level L : LOW Voltage Level pn (qn) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X : Immaterial
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC194
Timing Diagram
CP Mode Control Inputs S1 MR Parallel Data Inputs DSH DSL P0 Parallel Data Inputs P2 P3 Q0 Outputs Q1 Q2 Q3 Shift Right Clear Load Shift Left Inhibit Clear H L P1 H L S0
Absolute Maximum Ratings
Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V Condition
Recommended Operating Conditions
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC194
DC Characteristics
Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* Quiescent supply current IIN IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- 8.0 Ta = -40 to +85C min. max. 2.1 -- 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 80 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition
Input Voltage
V
VOUT = 0.1 V or VCC -0.1 V
Output voltage
VOH
VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics
Ta = +25C CL = 50 pF Min Typ Max 75 100 1.0 1.0 1.0 1.0 1.0 1.0 -- -- -- -- -- -- -- -- 13.0 10.0 13.0 10.0 10.5 8.0 Ta = -40C to +85C CL = 50 pF Min Max 65 85 1.0 1.0 1.0 1.0 1.0 1.0 15.0 11.5 15.0 11.5 12.5 9.0 MHz ns ns ns
Item Maximum clock frequency Propagation delay CP to Qn Propagation delay CP to Qn Propagation delay MR to Qn Note:
Symbol fmax tPLH tPHL tPHL
VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Unit
1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC194
AC Operating Requirements
Ta = +25C CL = 50 pF Item Setup time, HIGH or LOW Pn or DSR or DSL to CP Hold time, HIGH or LOW Pn or DSR or DSL to CP Setup time, HIGH or LOW Sn to CP Hold time, HIGH or LOW Sn to CP Recovery time MR to CP Pulse width Note: Symbol VCC (V)*1 tsu 3.3 -- th tsu th trec tw 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V -- -- -- -- -- -- -- -- -- -- -- Typ Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns ns ns
Guaranteed Minimum 5.5 7.0 4.0 2.0 1.5 6.0 4.5 0.0 0.0 0.5 0.5 5.5 4.5 5.0 3.0 2.0 7.5 5.5 0.0 0.0 0.5 0.5 7.0 5.0
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 100 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC194
Package Dimensions
As of January, 2003
10.06 10.5 Max 16 9
5.5
Unit: mm
1
*0.20 0.05
8
0.80 Max
2.20 Max
0.20 7.80 + 0.30 -
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9 10.3 Max 16 9
3.95
1 1.27 0.635 Max
8
0.11 0.14 + 0.04 - 1.75 Max
*0.20 0.05
0.10 6.10 + 0.30 -
1.08
0 - 8
+ 0.67 0.60 - 0.20
*0.40 0.06
0.15 0.25 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-16DNV Conforms Conforms 0.15 g
Rev.2.00, Jul.16.2004, page 7 of 7
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